1. Field of the Invention
The present invention relates to devices and methods of exchanging data, and, in particular, to systems of data exchanging between system-on-a-chip (SoC) and nonvolatile NAND Flash memory with sequential access and loading of firmware for system-on-a-chip of a GNSS receiver from this memory.
2. Discussion of the Related Art
A typical system-on-a-chip (SoC), including an SoC of a GNSS receiver, is a microchip based on a silicon die. One or more processing cores (PC) with different purposes (e.g., CPU, DSP), an internal volatile RAM, target Intellectual Property cores (IP-cores) and peripheral interface controllers IP-cores which served for interacting SoC with external devices, are located on the die. One or more internal busses are used to connect cores in the SoC one to another.
Information needed for SoC operation is stored, as rule, in nonvolatile memory capable of saving the information when power is off. The most efficient type of nonvolatile memory available on the market at the moment is NAND Flash memory. A distinguishing feature of the NAND Flash memory is its sector organization, i.e., data writing and reading is executed by continuous blocks of a fixed size (sectors). The sector in NAND Flash memory array can have two parts: the main part, and additional ones. The main sector part, with a size from 512 up to 2048 bytes, is intended for data storage. The additional part, with a size of a few tens of bytes, is used to keep extra information related to the content of the main part. The additional part can store a check sum of the main division content, including error correction code, sector's file system mark, and so on.
In manufacturing large-capacity NAND Flash memory modules, a manufacturer does not individually test each sector of each produced module to detect bad memory elements. Manufacturers guarantee only a maximum number of bad elements that is not to be exceeded in each individual module of specific capacity and type. The location of these bad elements within the array of storage elements is not specified. Most manufacturers of NAND Flash also guarantee that one sector (typically, it is the sector with address 0x00) has no bad storage elements after each NAND Flash module has been produced and packaged. This means that the probability of no failures for this sector after the first operation of data recording made with adherence to the specified technological limitations is close to 100%.
It should be noted that external access to a separate data element (byte, word, etc) inside a sector of the memory module is impossible for most NAND Flash modules. Some manufacturers provide such access in NAND Flash microchips thanks to enhancements of the controller built into the NAND Flash module, integration of extra buffer RAMs, and incorporation of special commands for address access to particular bytes, into NAND Flash control instructions.
Capabilities of hardware protection for data stored in the NAND Flash elements from accidental erasure or overwriting are very limited. As rule, such protection is implemented as an input hardware signal Write Protect (WP) which is a part of the external interface of a NAND Flash memory module. When activated, the WP signal inhibits any writing or erasing command for the entire array of storage elements inside the module, making it possible only to read the contents.
The contents of each sector is read or written in the NAND Flash memory module as sequential messages, whose bit size matches the physical width of the bidirectional data bus in the NAND Flash memory module. An initial address in the memory array, starting, from which the read or written sector is located, is transmitted via the same bus. This access method is called the sequential access to a data array.
Sequential access is different from random access, which allows addressing arbitrary separate elements of the memory array (bytes, words, etc.), the elements being read or written in a random order. Most CPUs can directly work only with random access memory which has physically separated address and data busses, for example internal RAM of a SoC. The NAND controller, which is between the SoC bus and NAND Flash memory module, provides the CPU with addressing to NAND Flash memory with sequential access. The NAND-controller is designed for generating a sequence of commands, addresses and auxiliary signals needed for addressing NAND Flash memory module, as well as for converting a data block from a random access format into sequential access format to write/read information to/from NAND Flash and vice versa (from a sequential access format into a random access format).
The SoC CPU starts operating when the active level of the CPU restart signal, generated earlier from both internal and external devices within SoC, has been cleared. The CPU executes program code, which is at the address of the system bus starting from a previously-assigned address. This code (with the corresponding starting address) can be located both in the random access ROM connected to the system bus and in a volatile RAM. In the latter case, the volatile RAM should have proper firmware (execution code) written to it by the time the CPU starts operation. The code should be located starting from a pre-defined address. The procedure of copying the execution code is called the SoC booting routine.
FW (firmware) booting routine implemented in most modern systems-on-a-chip can be described as a combination of two possible approaches to executing this procedure. The first one uses a ROM module with random access in the SoC, which is connected to the system bus and contains the booting code. As soon as the active level of the restart signal is cleared, the CPU executes code from the address space of the module, which controls copying a target FW from external or internal nonvolatile memory into internal RAM. After completing the copy process, the CPU starts executing the target FW from its internal RAM.
The second approach connects a special booting module with a finite-state machine (FSM) to the SoC system bus. The FSM takes control over the interface IP-core with nonvolatile memory and copies target FW from the nonvolatile memory into an internal SoC RAM. In the process of copying, the booting module keeps the CPU in the reset state by setting the restart signal to an active state. The active level of the CPU restart signal is cleared after copy operation has been completed, and then the CPU starts executing the code of the target FW from the internal RAM.